1. Field of the Invention
The present invention relates to a method of IC manufacturing, and in particular, to a method of manufacturing a superjunction structure.
2. Description of Related Art
It is known that a superjunction structure as shown in FIG. 1 is often used as a power MOSFET having both high withstand voltage and low on resistance. In FIG. 1, an N type region 2 is formed on a semiconductor substrate 1. P type regions 3 are filled in the N type region 2 to form alternating P type and N type regions. A body contact region 5, a source region 6, and a P+ implantation region 7 are arranged at both sides of each P type region 3 from outside in. Gate insulating films and gate electrodes 4 are formed on the N type region 2. Insulating films 8 are deposited on the gate electrodes 4. A source metal electrode 9 is formed to cover the insulating films 8 and the P type regions 3. A drain electrode 10 is formed on the backside of the semiconductor substrate 1.
It is not easy to manufacture the aforementioned superjunction structure, especially the alternately arranged P type 3 an N type 2 pillars. In the prior art, there are mainly two methods of manufacturing superjunction structures.
The first method of manufacturing superjunction structure is shown in FIG. 2. Firstly, grow a 1st N type epitaxial layer 22a on a substrate 21, afterwards, implant P type dopants into the 1st N type epitaxial layer to form a 1st implantation region 23a. Secondly, grow a 2nd N type epitaxial layer 22b on the 1st N type epitaxial layer, and then, implant P type dopants into the 2nd N type epitaxial layer 22b to form a 2nd implantation region 23b. Repeat the steps of epitaxial growth and implantation until the thickness of the N type epitaxial layer meets the requirement, wherein, the implantation regions are vertically aligned with one another. Finally, diffuse the P type dopants to form a P type pillar 25 by anneal. In this way, a complete P (or N) type pillar is finished.
The problems of the first method include: high cost, since epitaxial growth and implantation are both processes of high cost in semiconductor manufacturing; difficulty in process control, as the several times of epitaxial growth require the same resistivity and film quality; requirement of high alignment accuracy, since the dopants are required to be implanted at the same position.
Another method of manufacturing superjunction structure is shown in FIG. 3. Firstly, grow a thick N type epitaxial layer 32 on the substrate 31. Secondly, etch the N type epitaxial layer 32 to form trenches 35. Thirdly, fill P type epitaxial material 33 in the trenches 35 by P type epitaxial filling process. Finally, planarize the top of the trenches 35 by CMP process. The cost of this manufacturing method is lower than the first method, but voids and defects are easily formed in the trenches during the step of epitaxial filling due to the difference between the growth speed at the top of the trenches and the growth speed at the bottom of the trenches. Such voids and defects will have great impact on the performance of the device.